S29CD032J datasheet(52/81 Pages) SPANSION

52 / 81 page

S29CD-J and S29CL-J Flash Family

S29CD-J_CL-J_00_B7 October 11, 2012

Da ta

Sh e e t

Caution

Entering standby mode via the RESET# pin also resets the device to read mode and floats the data I/O pins.

Furthermore, entering ICC7 during a program or erase operation leaves erroneous data in the address

locations being operated on at the time of the RESET# pulse. These locations require updating after the

device resumes standard operations. See Hardware RESET# Input Operation on page 52for further

discussion of the RESET# pin and its functions.

12.2

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The automatic sleep mode is

independent of the CE#, WE# and OE# control signals. While in sleep mode, output data is latched and

always available to the system.

While in asynchronous mode, the device automatically enables this mode when addresses remain stable for

tACC + 60 ns. Standard address access timings provide new data when addresses are changed. While in

synchronous mode, the device automatically enables this mode when either the first active CLK level is

greater than tACC or the CLK runs slower than 5 MHz. A new burst operation is required to provide new data.

ICC8 in DC Characteristic, CMOS Compatible on page 54 represents the automatic sleep mode current

specification.

12.3

Hardware RESET# Input Operation

The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#

is driven low, the device immediately terminates any operation in progress, tristates all outputs, resets the

configuration register, and ignores all read/write commands for the duration of the RESET# pulse. The device

also resets the internal state machine to reading array data. Any operation that was interrupted should be

reinitiated once the device is ready to accept another command sequence, in order to ensure data integrity.

When RESET# is held at VSS ±0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at

VIL but not within VSS ±0.2 V, the standby current is greater.

RESET# may be tied to the system reset circuitry, thus a system reset would also reset the Flash memory,

enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains low until the reset

operation is internally complete. This action requires between 1 µs and 7 µs for either Chip Erase or Sector

Erase. The RY/BY# pin can be used to determine whether the reset operation is complete. Otherwise, allow

for the maximum reset time of 11 µs.

If RESET# is asserted when a program or erase operation is not executing (RY/BY# = 1), the reset operation

completes within 500 ns. The Simultaneous Read/Write feature of this device allows the user to read a bank

after 500 ns if the bank is in the read/reset mode at the time RESET# is asserted. If one of the banks is in the

middle of either a program or erase operation when RESET# is asserted, the user must wait 11 µs before

accessing that bank.

Asserting RESET# active during VCC and VIO power up is required to guarantee proper device initialization

until VCC and VIO have reached steady state voltages.

12.4

Output Disable (OE#)

When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high

impedance state.

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