M24LR16E-R datasheet(37/143 Pages) STMICROELECTRONICS

Part #	M24LR16E-R

Description	16-bit EEPROM with password protection, dual interface & energy harvesting: 400 kHz I²C bus & ISO 15693 RF protocol at 13.56 MHz

PDF	143 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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37 / 143 page

M24LR16E-R

I2C device operation

Doc ID 018932 Rev 8

37/143

5.10

Minimizing system delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum I²C write time (tw) is

shown in Table 123, but the typical time is shorter. To make use of this, a polling sequence

can be used by the bus master.

The sequence, as shown in Figure 10, is:

Initial condition: a write cycle is in progress.

Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus

master goes back to Step 1. If the device has terminated the internal write cycle, it

responds with an Ack, indicating that the device is ready to receive the second part of

the instruction (the first byte of this instruction having been sent during Step 1).

M24LR16E-R Datasheet(PDF) 37 Page - STMicroelectronics