Note 1)

2 bits (CPU clock selection).

Note 2) CS, SCK, SI and SO represent CS0, SCK0, SI0 and SO0 for CH0; they represent CS1, SCK1, SI1

and SO1 for CH1, respectively.

Note 3) The load of SCK output mode and SO output delay time is 50pF.

– 21 –

CXP84716/84720/84724

Serial transfer (CH0, CH1)

CS

↓ → SCK

delay time

CS

↑ → SCK

floating delay time

CS

↓ → SO delay time

CS

↑ → SO floating

delay time

CS High level width

2

8000/fc

4000/fc – 100

–

200

2

100

1.5

1.5

1.5

1.5

2

125

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Item

Symbol

Pin

Conditions

Min.

Max.

Unit

Chip select transfer mode

(SCK = output mode)

Chip select transfer mode

(SCK = output mode)

Chip select transfer mode

Chip select transfer mode

Chip select transfer mode

Input mode

Output mode

Input mode

Output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK input mode

SCK output mode

SCK cycle time

SCK High and Low

level widths

SI input setup time

(for SCK

↑)

SI input hold time

(for SCK

↑)

SCK

↓ → SO

delay time

SCK0

SCK1

SCK0

SCK1

SO0

SO1

SO0

SO1

CS0

CS1

SCK0

SCK1

SCK0

SCK1

SI0

SI1

SI0

SI1

SO0

SO1