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CXP88340 Datasheet(PDF) 21 Page - Sony Corporation |
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CXP88340 Datasheet(HTML) 21 Page - Sony Corporation |
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21 / 34 page ![]() – 21 – CXP88340/88348 Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. (2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item CS0 ↓ → SCK0 delay time CS0 ↑ → SCK0 floating delay time CS0 ↓ → SO0 delay time CS0 ↑ → SO0 floating delay time CS0 high level width SCK0 cycle time SCK0 high and low level widths SI0 input set-up time (against SCK0 ↑) SI0 input hold time (against SCK0 ↑) SCK0 ↓ → SO0 delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 ns ns ns ns ns Symbol Pins Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2 tsys + 200 16000/fc tsys + 100 8000/fc – 100 – tsys + 100 200 2 tsys + 100 100 ns ns ns ns ns ns ns ns ns ns 2 tsys + 100 100 Max. Unit Conditions |
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