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WM8232GEFL/V Datasheet(PDF) 8 Page - Wolfson Microelectronics plc |
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WM8232GEFL/V Datasheet(HTML) 8 Page - Wolfson Microelectronics plc |
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8 / 15 page ![]() WM8232 Product Brief w Product Brief, Rev 3.0, February 2012 8 ELECTRICAL CHARACTERISTICS Test Conditions AVDD = LDOVDD = DBVDD = 3.3V , AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 35MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions) Conversion rate per channel 5 35 MSPS Full-scale input voltage range (see Note 1) ADCFS=0, Max Gain ADCFS=0, Min Gain 0.12 2.0 Vp-p Vp-p ADCFS=1, Max Gain ADCFS=1, Min Gain 0.18 3.0 Vp-p Vp-p Input signal limits (see Note 2) VIN SF_INP=0 AGND-0.3 AVDD+0.3 V SF_INP=1 AGND AGND+1.2 V Input capacitance CIN Inputs to AGND 10 pF Full-scale transition error Gain = 0dB; AGAIN[4:0] = 02(hex) DGAIN[11:0] = 6AB(hex) 20 mV Zero-scale transition error Gain = 0dB; AGAIN[4:0] = 02(hex) DGAIN[11:0] = 6AB(hex) 20 mV Differential non-linearity DNL 10-bit 0.5 LSB Integral non-linearity (pk-pk/2) INL 10-bit 1 LSB Channel to channel gain matching Min Gain 5 % Max Gain 15 % Output noise Unity Gain (Unused channels grounded) 0.3 LSB rms Channel to channel crosstalk 10-bit +/-0.5 LSB Programmable Gain Amplifier Total Resolution (Ga + Gd) GT 12 bits Analogue Gain Ga 0.6 + 0.3 * AGAIN[4:0] V/V Max gain, each channel (Ga) Ga MAX AGAIN[4:0] = 1F(hex) 9.9 V/V Min gain, each channel (Ga) Ga MIN AGAIN[4:0] = 0(hex) 0.6 V/V Digital Gain Gd DGAIN[11:0] / 2 11 V/V Max gain, each channel (Gd) Gd MAX DGAIN[11:0] = FFF(hex) 2 V/V Min gain, each channel (Gd) Gd MIN DGAIN[11:0] = 400 (hex) 0.5 V/V Max gain, each channel (Ga + Gd) GTMAX AGAIN[4:0] = 1F(hex) DGAIN[11:0] = FFF(hex) 19.8 V/V Min gain, each channel (Ga + Gd) GTMIN AGAIN[4:0] = 0(hex) DGAIN[11:0] = 400 (hex) 0.3 V/V Analogue to Digital Converter Resolution 16 bits Speed 70 MSPS Notes: 1. Full-scale input voltage denotes the differential input signal amplitude (VIN-VRLC in non-CDS mode, VIN-RESET level in CDS mode) that can be gained to match the ADC full-scale input range. 2. Input signal limits are the limits within which each input voltage and VRLC reference must lie. |
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