WM8232

Product Brief

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Product Brief, Rev 3.0, February 2012

10

Test Conditions

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

CMOS Outputs

High level output voltage

AVDD

– 0.5

V

Low level output voltage

0.5

V

High impedance output current

1

A

TG Outputs

High level output voltage

AVDD

– 0.5

V

Low level output voltage

0.5

V

High impedance output current

Grounded

1

A

Digital IO Pins

Applied high level input voltage

0.7



AVDD

V

Applied low level input voltage

0.2



AVDD

V

High level output voltage

AVDD

– 0.5

V

Low level output voltage

0.5

V

Low level input current

1

A

High level input current

1

A

Input capacitance

5

pF

Output Impedance

Ro

Io = 1mA

38

Ω

High impedance output current

1

A

LVDS Outputs

Differential load impedance

RL

90

100

110

Ω

Differential steady-state output

voltage magnitude

|VOD|

RL=100Ω

280

450

mV

Change in the steady-state

differential output voltage

magnitude between opposite

binary states

Δ|VOD|

RL=100Ω

15

mV

Steady-state common-mode

output voltage

VOC(SS)

RL=100Ω

1.25

V

Peak-to-peak common-mode

output

VOC(PP)

20

50

mV

Short-circuit output current

IOS

–6

6

mA

High-impedance state output

current

IOZ

–10

10

uA

Supply Currents



Total supply current

 active

SF_INP=0, SF_VRLC=0

230

mA

SF_INP-1, SF_VRLC=1

250

m



Total supply current

 full power

down mode

1.0

m



Notes:

1.

Full-scale input voltage

level in CDS mode) that can be gained to match the ADC full-scale input range.

2.

Input signal limits

are the limits within which each input voltage and VRLC reference must lie.