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LCX032AKB

2. LCD Panel Operations

• Through current of the level shifter during power supply cutoff can be reduced by STB pin. (power save

mode)

Power save mode is set at STB = Low level.

• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse

to every 218 gate lines sequentially in every horizontal scanning period. A vertical shift register scans the

gate lines from the top to bottom of the panel at DWN = High level.

• The selected pulse is delivered when the enable pin turns to High level. PAL mode images are displayed by

controlling the enable and VCK pin. The enable pin should be High when not in use.

• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits

applies selected pulses to every 521 signal electrodes sequentially in a single horizontal scanning period.

• Vertical and horizontal drivers address one pixel and then turn on Thin Film Transistors (TFTs; two TFTs) to

apply a video signal to the dot. The same procedures lead to the entire 218

× 521 dots to display a picture in

a single vertical scanning period.

• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned with 1.5-dot shifted

against adjacent horizontal line. 1.5-dot shift of a horizontal driver output pulse against horizontal

synchronized signal is required to apply a video signal to each dot properly. 1H reversed displaying mode is

required to apply video signal to the panel.

• The video signal shall be input with polarity-inverted system in every horizontal cycle.

• Timing diagrams of the vertical and the horizontal right-direction scanning (RGT = High level) display cycle

are shown below: