CBTL06DP212

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 2 — 3 November 2011

4 of 18

NXP Semiconductors

CBTL06DP212

High-performance DisplayPort Gen2 2 : 1 multiplexer

7.

Pinning information

7.1 Pinning

Fig 2.

Pin configuration for TFBGA48

Transparent top view

Fig 3.

Ball mapping

002aaf879

Transparent top view

CBTL06DP212EE

H

J

G

F

E

D

C

A

B

2468 9

1357

ball A1

index area

1

A

002aaf943

GPU_SEL

VDD

IN1_0

−

IN1_1

−

IN1_2

−

IN1_3+

IN1_3

−

23

456

789

B

OUT_0

−

OUT_0+

GND

IN1_0+

IN1_1+

IN1_2+

TST0

IN2_0+

IN2_0

−

C

DDC_AUX

_SEL

GND

D

OUT_1

−

OUT_1+

IN2_1+

IN2_1

−

E

OUT_2

−

OUT_2+

IN2_2+

IN2_2

−

F

OUT_3

−

OUT_3+

IN2_3+

IN2_3

−

G

GND

GND

H

AUX

−

AUX+

HPD_2

GND

DDC_CLK2

AUX2+

GND

DDC_CLK1

AUX1+

J

HPDIN

HPD_1

VDD

DDC_DAT2

AUX2

−

DDC_DAT1

AUX1

−