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AD1892 Datasheet(PDF) 2 Page - Analog Devices

Part # AD1892
Description  Integrated Digital Receiver/Rate Converter
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD1892 Datasheet(HTML) 2 Page - Analog Devices

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TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltage
+5.0
V
Ambient Temperature
25
°C
Output Sample Frequency (FSOUT)
48.8
kHz
MCLK
25
MHz (512
× F
SOUT)
Input Word Width
20
Bits
Load Capacitance
100
pF
All minimums and maximums tested except as noted.
PERFORMANCE1
Min
Typ
Max
Units
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
120
dB
Total Harmonic Distortion + Noise
(20 Hz to 20 kHz, Full-Scale Input)
–103
dB
(1 kHz Full-Scale Input)
–113
dB
(10 kHz Full-Scale Input)
–107
dB
Interchannel Phase Deviation
0
Degrees
DIGITAL I/O1
Min
Typ
Max
Units
VIH
2.4
V
VIL
0.8
V
IIH @ VIH = +5.0 V
10
µA
IIL @ VIL = 0 V
10
µA
VOH @ IOH = –0.5 mA
DVDD – (0.5)
V
VOL @ IOL = 0.5 mA
0.5
V
Input Capacitance
1
15
pF
DIGITAL TIMING1
Min
Typ
Max
Units
tMCP
MCLK Duty Cycle
1
40
60
%
FMCLK
MCLK Frequency (1/tMCP)
1
25
MHz
tPDRP
PD/RST LO Pulsewidth
10
× MCLK Period
ns
tBDM
BCLK Propagation Delay from MCLK (to Falling Edge)
30
ns
tLDM
L
RCLK Propagation Delay from MCLK
30
ns
tDDP
Data Propagation Delay from MCLK
30
ns
tDDS
Data Output Setup to BCLK
1/2 BCLK Period
ns
tDDH
Data Output Hold from BCLK
1/2 BCLK Period
ns
tSSU
SYNC Falling Setup to MCLK Rising
5
ns
tCCH
CCLK HI Pulsewidth
20
ns
tCCL
CCLK LO Pulsewidth
20
ns
tCCP
CCLK Period
8
× MCLK Period
ns
tCSU
SDI Setup
15
ns
tCHD
SDI Hold
10
ns
tCOH
SDO Propagation Delay from CCLK
30
ns
tSFPW
SFCLK HI Pulsewidth
1
100
ns
tSFSU
U/CBIT, INT, ERROR Setup to SFCLK
100
ns
tCSPW
CSCLK HI Pulsewidth
1
100
ns
tQDH
QDFS HI Pulsewidth
1
1000
ns
tCLH
CS HI Pulsewidth
10
× MCLK Period
ns
tCLK
CS Falling Edge to CCLK Rising
3
× MCLK Period
ns
tRS
PD/RST Rising to MCLK Rising Edge (Only Required
for Synchronizing Multiple Parts)
5
ns
DIGITAL RS-422 RECEIVERS (RXP, RXN Pins Only)
Min
Typ
Max
Units
Input Resistance
20
k
Ω
Min Differential AES/EBU or S/PDIF Input
200
mV p-p
Input Hysteresis
20
mV
AD1892–SPECIFICATIONS
REV. 0
–2–



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