AD1892 datasheet(21/24 Pages) AD

21 / 24 page

AD1892

REV. 0

–21–

Dither

The AD1892 can be programmed to add triangular Probability

Distribution Function (PDF) dither to the digital audio samples. It

is advisable to add dither when the input word width exceeds

the output word width, e.g., the input word is 20 bits and the

output word is 16 bits. Triangular PDF is generally considered

to create the most favorable noise shaping of the residual

quantization noise. The AD1892’s dither function is always

available, even when the part is configured in bypass mode.

Asynchronous Sample Rate Converter

The AD1892 uses a different Asynchronous Sample Rate

Conversion (ASRC) algorithm than the AD1890/AD1891/

AD1893. The upsampling range is much wider (1:5, from

10 kHz to 48 kHz continuous), but the downsampling range is

more constrained (48 kHz down to 44.1 kHz, without significant

artifacts). Unlike the AD1890/AD1891/AD1893, the AD1892’s

rate converter does not include automatic input frequency band-

limiting, which places constraints on artifact-free downsampling.

Program material sampled at 48 kHz can theoretically have

frequency content up to 24 kHz; when this is downsampled to

44.1 kHz, there can be aliased spectral energy from 20.1 kHz to

24.1 kHz, which is not fully attenuated by the AD1892’s digital

filter. For example, a full-scale 24 kHz signal would be attenuated

by –6 dB when resampled to 44.1 kHz.

The AD1892 ASRC performs 128 times interpolation, low-pass

filtering, and resampling (decimation) at the MCLK/512 (i.e.,

FSOUT) rate. The digital filter passband ripple is

±0.015 dB, and

the transition band extends from 20 kHz to 24.1 kHz. The

stopband attenuation is 120 dB.

DAT Start ID

The AD1892 status register provides a bit that is intended to be

used in Digital Audio Tape (DAT) systems to facilitate the

location of the beginning of tracks. In DAT systems, when the

category code is set to DAT (i.e., 1100000) and the first right

subframe user bit in a DAT frame (identified as “R0’’ in the

IEC-958 documents) is set to 1, this is an indication of the start

of a new track. The AD1892 will set Bit D7 in Status Register 1

HI when the category code is 1100000 and any received right

channel subframe user bit is 1. This bit is sticky and will stay set

until Status Register 1 is read.

Coding Violation Status Bit

The AD1892 includes a bit (D0 in Status Register 0) that is set

HI when the AD1892 encounters biphase-mark encoding error,

other than X, Y or Z preambles, in the input serial stream. This

bit is sticky and will stay set until Status Register 0 is read. This

bit can be used to monitor the integrity of the biphase-mark

interconnect feeding the AD1892.

Q-Channel Block Start Status Bit and QDFS Signal

The AD1892 provides two indications that a Q-Channel sub-

code block start has been encountered in consumer mode.

There is a bit (D5 in Status Register 1) that is set HI after the

subcode synchronization word (S0 + S1) has been received.

This bit is sticky and will stay set until Status Register 1 is read.

There is also an output signal QDFS (Pin 6) that is asserted

when the subcode sync word has been received. QDFS goes HI

for one subframe period.

Word Width

The AD1892 can use up to 20 bits of incoming audio data, i.e.,

all of the bits from Bit 8 through Bit 27 in each subframe. The

serial digital audio standards allow the use of the so-called “Aux

Data” bits to extend the audio data word length to 24 bits;

however, the AD1892 does not support this word length extension.

Mono Output Control Register Option

A monaural (mono) output can be provided by the AD1892

using the mono mode Bit D6 in Control Register 1. When this

bit is set to 1, the AD1892 puts (Right Channel + Left Channel)/2

on both the left and right channel serial data output. Adding

both channels together and dividing by 2 has the effect of

lowering the perceived amplitude of resulting output for largely

uncorrelated right and left channel input material, but also

avoids the possibility of clipping with highly correlated right and

left channel input material.

Microcontroller Applications

In many systems, the AD1892 will be used with an external

microcontroller to enable the more sophisticated functions of

which the device is capable. The microcontroller servicing the

AD1892 should follow the following suggestions:

1. The microcontroller should read (and thereby clear) the

status registers after initial start-up. The microcontroller

should wait until the NOSIG pin is deasserted LO before

clearing Status Register 0 and 1. This procedure will avoid

the problems of invalid channel status and Q-Channel

subcode CRC errors, invalid parity and validity errors, in-

valid coding violations errors, etc. All other status bits are

invalid when No Phase Lock (Bit D7, Status Register 0) is 1

(no phase lock), so all errors should be ignored by the micro-

controller until this bit is deasserted LO.

2. The Q-Channel subcode CRC error indication (Bit D6,

Status Register 1) is not valid until subcode sync is achieved.

Subcode sync is indicated when Q Channel Block Start (Bit

D5, Status Register 1) is 1 or when the QDFS signal (Pin 6)

is asserted HI.

3. The AD1892 updates its on-chip channel status buffer and Q

Channel subcode buffer regardless of whether or not CRC

errors are detected. The system engineer must decide if the

microcontroller should update its information (i.e., read the

AD1892 status buffers) when channel status CRC errors

occur in professional mode or when Q Channel subcode

CRC errors occur in consumer mode.

AD1892 Datasheet(PDF) 21 Page - Analog Devices

AD1892 Datasheet(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL