MAX11166 datasheet(21/33 Pages) MAXIM

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MAX11166/MAX11167

16-Bit, 500ksps/250ksps, ±5V SAR ADCs

with Internal Reference in TDFN

www.maximintegrated.com

Input Configuration Interface

An SPI interface clocked at up to 50MHz controls the

MAX11166/MAX11167. Input configuration data is clocked

into the configuration register on the falling edge of SCLK

through the DIN pin. The data on DIN is used to program

the ADC configuration register. The construct of this reg-

ister is illustrated in Table 4. The configuration register

defines the output interface mode, the reference mode,

and the power-down state of the MAX11166/MAX11167.

Configuring in CS Mode

Figure 4 details the timing for loading the input configuration

mode (see Figure 6 and Figure 8 for hardware connec-

tions). The load process is enabled on the falling edge of

CNVST when SCLK is held high. The configuration data is

clocked into the configuration register through DIN on the

next 8 SCLK falling edges. Pull CNVST high to complete

the input configuration register load process. DIN should

idle high outside an input configuration register read.

Table 4. ADC Configuration Register

Figure 4. Input Configuration Timing in CS Mode

BIT NAME

BIT

DEFAULT

STATE

LOGIC

STATE

FUNCTION

MODE

7:6

CS Mode, No-Busy Indicator

CS Mode, with Busy Indicator

Daisy-Chain Mode, No-Busy Indicator

Daisy-Chain Mode, with Busy Indicator

REF

5:4

Reference Mode 0. Internal reference and reference buffer are both

powered on.

Reference Mode 1. Internal reference is turned off, but internal reference

buffer powered on. Apply the external reference voltage at REFIO.

Reference Mode 2. Internal reference is powered on, but the internal

reference buffer is powered off. This mode allows for internal reference to

be used with an external reference buffer.

Reference Mode 3. Internal reference and reference buffer are both

powered off. Apply an external reference voltage at REF.

SHDN

Normal Mode. All circuitry is fully powered up at all times.

Static Shutdown. All circuitry is powered down.

Reserved

2:0

Reserved, Set to 0

01234

tHSCKCNF

tSSCKCNF

CNVST

SCLK

DIN

tHDINSCK

tSDINSCK

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