MMA9550LT datasheet(21/25 Pages) FREESCALE

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MMA955xL

Sensors

Freescale Semiconductor, Inc.

4.14

I2C Timing

This device includes a slave I2C module that can be used to control the sensor and can be active 100 percent of the time. It also

includes a master/slave I2C module that should be used only during CPU run mode (

ΦD).

Figure 12. I2C standard and fast-mode timing

4.14.1

Slave I2C

4.14.2

Master I2C Timing

The master I2C module should only be used when the system clock is running at full rate. Do not attempt to use the master I2C

module across frames in which a portion of the time is spent in low-speed mode.

Table 13. I2C Speed Ranges

Mode

Max Baud

Rate (fSCL)

Minimum

Bit Time

Minimum SCL Low

(tLOW)

Minimum SCL High

(tHIGH)

Min Data setup Time

(tSU; DAT)

Min/Max Data Hold Time

(tHD; DAT)

Standard

100 KHz

μs4.7 μs4 μs

250 ns

μs/3.45 μs(1)

The maximum tHD; DAT must be at least a transmission time less than tVD;DAT or tVD;ACK. For details, see the I

2C standard.

Fast

400 KHz

2.5

μs1.3 μs0.6 μs

100 ns

μs/0.9 μs(1)

Fast +

1 MHz

μs

500 ns

260 ns

50 ns

μs/0.45 μs(1)

High-speed

supported

2.0 MHz

0.5

μs

200 ns

10 ns(2)

0 ns/70 ns (100 pf)(2)

Timing met with IFE = 0, DS = 1, and SE = 1. See the “Port Controls” chapter in the MMA955xL Three-Axis Accelerometer Reference Manual

(MMA955xLRM).

Table 14. Master I2C timing

Characteristic

Symbol

Standard Mode

Fast Mode

Unit

Min

Max

Min

Max

SCL clock frequency

fSCL

100

400

kHz

Hold time (repeated) START condition. After this period, the first

clock pulse is generated.

tHD; STA

4.0

—

0.6

—

μs

LOW period of the SCL clock

tLOW

4.7

—

1.3

—

μs

HIGH period of the SCL clock

tHIGH

4.0

—

0.6

—

μs

Setup time for a repeated START condition

tSU; STA

4.7

—

0.6

—

μs

Data hold time for I2C-bus devices

tHD; DAT

0(1)

The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a neg-

ative hold time can result, depending on the edge rates of the SDA and SCL lines.

3.45(2)

The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

0(1)

0.9(2)

μs

Data setup time

tSU; DAT

250(3)

Setup time in slave-transmitter mode is one IPBus clock period, if the TX FIFO is empty.

—

100(3) (4)

A fast-mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This will automat-

ically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must

output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I

2C bus specification) before the SCL

line is released.

—ns

Setup time for STOP condition

tSU; STO

4.0

—

0.6

—

µs

Bus-free time between STOP and START condition

tBUF

4.7

—

1.3

—

µs

Pulse width of spikes that must be suppressed by the input filter

tSP

N/A

SDA

SCL

tHD; STA

tHD; DAT

tLOW

tSU; DAT

tHIGH

tSU; STA

tHD; STA

tSP

tSU; STO

tBUF

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