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MMA9550LT Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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MMA9550LT Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 25 page ![]() MMA955xL Sensors Freescale Semiconductor, Inc. 13 • Minimize PCB trace lengths for high-frequency signals. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. • Take special care to minimize noise levels on the VDDA and VSSA pins. • Use separate power planes for VDD and VDDA and separate ground planes for VSS and VSSA. Connect the separate analog and digital power and ground planes as close as possible to power supply outputs. If both analog circuit and digital circuits are powered by the same power supply, it is advisable to connect a small inductor or ferrite bead in series with both the VDDA and VSSA traces. • Physically separate the analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. It is also desirable to place an analog ground trace around an analog signal trace to isolate it from digital traces. • Provide an interface to the BKGD/MS pin if in-circuit debug capability is desired. • Ensure that resistors RP1 and RP2, in the following figure, match the requirements stated in the I 2C standard. For the shown configuration, the value of 4.7 k Ω would be appropriate. 3.4.3 MMA955xL Platform as an Intelligent Slave I2C pullup resistors, a ferrite bead, and a few bypass capacitors are all that are required to attach this device to a host platform. The basic configurations are shown in the following two figures. In addition, the RGPIO pins can be programmed to generate interrupts to a host platform in response to the occurrence of real-time application events. In this case, the pins should be routed to the external interrupt pins of the CPU. Figure 7. Platform as an I2C slave Quiet VDDA for best performance 1.8V 1.8V 1.8V 1.8V 1.8V C4 1μF C3 0.1μF U1 MMA955X 1 3 4 5 2 9 10 11 12 13 VDD RESETB SCL0/IO0/SCLK VSS BKGD/MS/IO9 IO4/INT VSS IO5/PDB_A/INT_O IO6/AN0 IO7/AN1 R2 4.7KΩ R3 4.7KΩ L1 10μFBEAD 1 2 C1 1μF C2 0.1μF R1 4.7KΩ R4 4.7KΩ INT_OUT I2C_CLK I2C_DATA |
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