AT45DB321D_12 datasheet(31/51 Pages) AD

31 / 51 page

AT45DB321D [DATASHEET]

3597R–DFLASH–11/2012

17.

Input Test Waveforms and Measurement Levels

tR, tF < 2ns (10% to 90%)

18.

Output Test Load

19.

AC Waveforms

Six different timing waveforms are shown on page 31. Waveform 1 shows the SCK signal being low when CS makes a high-to-

low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. In both cases, output

SO becomes valid while the SCK signal is still low (SCK low time is specified as tWL). Timing waveforms 1 and 2 conform to

RapidS serial interface, but for frequencies up to 66MHz. Waveforms 1 and 2 are compatible with SPI Mode 0 and SPI Mode 3,

respectively.

Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and

waveform 2, except that output SO is not restricted to become valid during the tWL period. These timing waveforms are valid

over the full frequency range (maximum frequency = 66MHz) of the RapidS serial case.

Table 19-1. Waveform 1 – SPI Mode 0 Compatible (for frequencies up to 66MHz)

Driving

Levels

Measurement

Level

0.45V

1.5V

2.4V

Device

under

test

30pF

SCK

tCSS

Valid in

tSU

tWH

tWL

tCSH

tCS

High impedance

Valid out

tHO

tDIS

High impedance

AT45DB321D Datasheet(PDF) 31 Page - Analog Devices

AT45DB321D Datasheet(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL