ADMC330

–17–

REV. 0

Table VII. Peripheral Register Map

Address

Offset

(HEX)

(Decimal)

Name

Bits Used

Function

0x2000

0

ADC1

[4..15]

ADC Results for V1

0x2001

1

ADC2

[4..15]

ADC Results for V2

0x2002

2

ADC3

[4..15]

ADC Results for V3

0x2003

3

ADCAUX

[4..15]

ADC Results for VAUX

0x2004

4

PIODIR

[0..7]

PIO Pins Direction Setting

0x2005

5

PIODATA

[0..7]

PIO Pins Input/Output Data

0x2006

6

PIOINTEN

[0..7]

PIO Pins Interrupt Enable

0x2007

7

PIOFLAG

[0..7]

PIO Pins Interrupt Status

0x2008

8

PWMTM

[0..11]

PWM Period

0x2009

9

PWMDT

[0..6]

PWM Deadtime

0x200A

10

PWMPD

[0..6]

PWM Pulse Deletion Time

0x200B

11

PWMGATE

[0..8]

PWM Gate Drive Configuration

0x200C

12

PWMCHA

[0..11]

PWM Channel A Pulsewidth

0x200D

13

PWMCHB

[0..11]

PWM Channel B Pulsewidth

0x200E

14

PWMCHC

[0..11]

PWM Channel C Pulsewidth

0x200F

15

PWMSEG

[0..8]

PWM Segment Select

0x2010

16

AUX0

[0..7]

AUX PWM Output 1

0x2011

17

AUX1

[0..7]

AUX PWM Output 2

0x2012

18

Not Used

0x2013

19

Not Used

0x2014

20

Not Used

0x2015

21

MODECTRL

[0..15]

System Control Register

0x2016

22

SYSSTAT

[0..1]

System Status

0x2017

23

IRQFLAG

[0..2]

Interrupt Status

0x2018

24

WDTIMER

[0..15]

Watchdog Timer

0x2019..F

25..31

Not Used

Multiplexer, PWM Interrupts and SPORT1 Control

The ADC, the SPORT1 peripherals and the PWM interrupts

are configured using the MODECTRL register.

1. Two bits control the ADC aux channel selection:

ADCMUX0..1.

2. Two bits can enable/disable the

PWMTRIP and PWMSYNC

interrupts.

3. Two bits control the SPORT1 UART and DR1A/B multiplexer.

The PWM interrupt enable bits are masking bits rather than

set/reset bits. Therefore, before enabling these interrupts any

pending interrupts can be cleared by reading the IRQFLAG

register.

Setting the UARTEN bit connects DR1 to the RFS1 input,

which allows SPORT1 to be used as a UART port. The DR1SEL

bit selects either pins DR1A or DR1B. The reset condition for

all bits in this register is zero.

ADMC330

SPORT1

DR1

TFS1

RFS1

DT1

DR1A

DR1B

DT1

SCLCK1

TFS1

RFS1

SCLCK1

UART

ENABLE

DR1B

SELECT

DEFAULT SWITCH

POSITION SHOWN

Figure 12. Internal Multiplexing of SPORT1 Pins

The DSP and Peripheral Reset Functions

A full system reset of the ADMC330 is achieved by pulling the

RESET pin low (for > 5 clock cycles when running, or > 2000

clock cycles on power-up). This resets the DSP core and all

peripherals including the watchdog timer.

The SYSSTAT register indicates the fault status of the ADMC330

after a

PWMTRIP interrupt or a watchdog reset:

1. The status of the

PWMTRIP pin (active low).

2. The status of the watchdog flag register (this is not reset on a

DSP

RESET).

3. The status of the PWMPOL pin.

When one of the peripherals generates an interrupt, the DSP

IRQ2 line is pulled low and a flag bit is set in the IRQFLAG

register for PWMSYNC and

PWMTRIP or in the PIOFLAG

register for a PIO interrupt. The DSP can read these registers to

determine the source of the interrupt. When the IRQFLAG

register is read, the PWMSYNC and

PWMTRIP bits are

cleared to zero. Reading the PIOFLAG register clears all the bits

in this register to zero. When both registers are cleared, the

IRQ2

line is set high again. The reset condition for all bits in this regis-

ter is zero.