REV. 0

ADP3510

–10–

TEMPERATURE – C

4.25

–40

4.24

4.23

4.22

4.21

4.20

4.19

4.18

4.17

4.16

4.15

–20

0

20

40

60

80

100 120

4.22

0

4.21

4.20

4.19

4.18

200

400

600

800

1000

INPUT VOLTAGE – V

4.210

5

4.205

4.200

4.195

4.190

67

89

10

THEORY OF OPERATION

The ADP3510 is a total solution power management chip for use

with CDMA baseband chipsets and is optimized for the CBP3.0/

4.0 type chipsets. Figure 1 shows a block diagram of the ADP3510.

The ADP3510 contains several blocks:

∑ Six Low Dropout Regulators (Input-Output, Core, Analog,

Crystal Oscillator, Memory, Realtime Clock)

∑ Reset Generator

∑ Buffered Precision Reference

∑ Lithium Ion Charge Controller and Processor Interface

∑ Power-On/-Off Logic

∑ Undervoltage Lockout

∑ Deep Discharge Lockout

These functions have traditionally been done either as a discrete

implementation or as a custom ASIC design. The ADP3510

combines the benefits of both worlds by providing an integrated

standard product where every block is optimized to operate in a

CDMA environment while maintaining a cost-competitive solution.

Figure 3 shows the external circuitry associated with the ADP3510.

Only a minimal number of support components are required.

Input Voltage

The input voltage range of the ADP3510 is 3.2 V to 7.5 V and is

optimized for a single Li-Ion cell or three NiMH cells. The thermal

impedance of the ADP3510 is 68

∞C/W for four layer boards. The

end of charge voltage for high capacity NiMH cells can be as high

as 5.5 V. Power dissipation should be calculated at maximum ambi-

ent temperatures and battery voltage in order not to exceed the 125

∞C

maximum allowable junction temperature. Figure 4 shows the maxi-

mum power dissipation as a function of ambient temperature.

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

ADP3510

ISENSE

DGND

GATEDR

GATEIN

CHRIN

CHRDET

MVBAT

PWRONIN

PWRONKEY

ROWX

ALARM

BATSNS

VRTC

PDCAP

EOC

CHGEN

RESCAP

RESET

VIO

VBAT2

VMEM

TCXOEN

AGND

REFOUT

VTCXO

VCORE

VBAT

VAN

PWRON

PWRONKEY

KEYPADROW

ALARM

VRTC

ADC

GPIO

GPIO

CHARGER IN

TCXOEN

VTCXO

VAN

REF

C3

1.0nF

R1

0.25

C2

10nF

C1

0.1 F

Q1

SI3441DY

D1

10BQ015

GPIO

GPIO

C5

0.1 F

C4

10 F

RESET

VCORE

VMEM

C8

2.2 F

C7

2.2 F

C6

2.2 F

R2 10

C9

2.2 F

C11

0.1 F

VIO

C10

0.22 F

Li

BATTERY

Figure 3. Typical Application Circuit