AD9119BBCZ datasheet(47/68 Pages) AD

47 / 68 page

Data Sheet

AD9119/AD9129

Rev. 0 | Page 47 of 68

The IRQ pin responds only to those interrupts that are enabled. To

clear an IRQ, it is necessary to write a 1b to the bit in Register 0x05

or Register 0x06 that caused the interrupt. See Figure 141 for

a detailed diagram of the interrupt circuitry.

The IRQ can also be used during the AD9119/AD9129

initialization phase after power-up to determine when the

retimer PLL and data receiver controllers achieve lock. For

example, before enabling the retimer PLL, the retimer lock

interrupt enable bit (Register 0x03[0]) can be set, and the IRQ

output signal can be monitored to determine when lock is

established, before continuing in a similar manner with the data

receiver controller. Clear the relevant lock bit, after locking, before

continuing to the next controller. When all of the controllers are

locked, set the appropriate lost lock enable bits in Register 0x03

to continuously monitor the controllers for loss of lock.

WRITE 1b TO

REQUEST BIT

IRQ ENABLE

SOURCE

IRQ REQUEST

IRQ ENABLE

IRQ PIN

SINGLE IRQ BIT

Figure 141. Interrupt Request Circuitry

Table 15. Interrupt Request Registers

Addr (Hex)

Bit

Bit Name

Description

0x05

FIFO_Warn2 interrupt status

Indicates that the FIFO is within two slots of overwrite

FIFO_Warn1 interrupt status

Indicates that the FIFO is within one slot of overwrite

SPIFrmAck interrupt status

Indicates acknowledgement that the SFrmReq bit has changed from 0b to 1b

Reserved

DLL warn interrupt status

Indicates that the DLL is close to coming unlocked and action is needed

DLL lock interrupt status

Indicates that the DLL is now locked

Retimer lost interrupt status

Indicates that the retimer PLL is no longer locked

Retimer lock interrupt status

Indicates that the retimer PLL is now locked

0x06

Reserved

AED pass interrupt status

Indicates that the AED logic has captured eight valid samples

AED fail interrupt status

Indicates that the AED logic has detected a miscompare

SED fail interrupt status

Indicates that the SED logic has detected a miscompare

Parity error falling edge status

Indicates a parity fault due to data captured on the falling edge

Parity error rising edge status

Indicates a parity fault due to data captured on the rising edge

Reserved

AD9119BBCZ Datasheet(PDF) 47 Page - Analog Devices

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