AD9119BBCZ datasheet(54/68 Pages) AD

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AD9119/AD9129

Data Sheet

Rev. 0 | Page 54 of 68

START-UP SEQUENCE

A small number of steps is required to program the AD9119/AD9129 to the proper operating state after the device is powered up. This

sequence is listed in Table 16, along with an explanation of the purpose of each step.

Table 16. Start-Up Sequence After Power-Up

Value

Description

0x00

4-wire SPI, MSB-first packing, short addressing mode

0x30

0x5C

Enable cross control, cross location = 7 dec, duty cycle correction off

0x0C

0x64

Set DLL minimum delay = 4 dec, enable DCO

0x0B

0x39

Set clock divider to DCI/512

0x01

0x68

Set bias power-down

0x34

0x6D or 0x5D

Set PLL mode for normal or 2× mode; normal mode or FIR25 on = 0x6D, FIR40 on = 0x5D

0x01

0x48

Enable bias

0x33

0x13

Initialize PLL to phase step = 1 dec

0x33

0xF8 or 0xD8

Select PFD, set PLL phase step, keep PLL lost bit cleared; phase step is as follows: normal mode or

FIR25 on = 0xF8, FIR40 on = 0xD8

0x33

0xF0 or 0xD0

Deassert the PLL lost bit, keeping the phase step; normal mode or FIR25 on = 0xF0, FIR40 on = 0xD0

0x0D

0x06

Set duty correction bandwidth to lowest

0x0A

0xC0

Enable DLL

0x18

0xm0

Select data mode, filter mode to set value of m; for example: 0x40, unsigned data, interpolator off

0x20

0xC6

Set full-scale current (FSC) to 33 mA

0x21

0x03

Complete the setting of FSC

0x30

0x46

Enable cross control, cross location = 1 dec, enable duty cycle correction

0x12

0x20

Set the FIFO pointers

0x11

0x81

Assert FIFO reset

0x11

0x01

Deassert FIFO reset

0x01

0x00

Enable IREF (DAC output)

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