 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PCF85063TP Datasheet(PDF) 32 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
PCF85063TP Datasheet(HTML) 32 Page - NXP Semiconductors |
|
|
32 / 46 page  PCF85063TP All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 2 — 15 April 2013 32 of 46 NXP Semiconductors PCF85063TP Tiny Real-Time Clock/calendar [1] A detailed description of the I2C-bus specification is given in Ref. 12 “UM10204”. [2] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second. Table 32. I2C-bus characteristics VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = 40 C to +85 C; fosc = 32.768 kHz; quartz Rs =60 k; CL = 7 pF; unless otherwise specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD[1]. Symbol Parameter Conditions Min Typ Max Unit Cb capacitive load for each bus line - - 400 pF fSCL SCL clock frequency [2] 0- 400 kHz tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tLOW LOW period of the SCL clock 1.3 - - s tHIGH HIGH period of the SCL clock 0.6 - - s tr rise time of both SDA and SCL signals 20 + 0.1Cb -0.3 s tf fall time of both SDA and SCL signals 20 + 0.1Cb -0.3 s tBUF bus free time between a STOP and START condition 1.3 - - s tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 0.6 - - s tVD;DAT data valid time 0 - 0.9 s tVD;ACK data valid acknowledge time 0 - 0.9 s tSP pulse width of spikes that must be suppressed by the input filter 0- 50 ns Fig 25. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 % SCL SDA tHD;STA tSU;DAT tHD;DAT tf tBUF tSU;STA tLOW tHIGH tVD;ACK 013aaa417 tSU;STO protocol START condition (S) bit 7 MSB (A7) bit 6 (A6) bit 0 (R/W) acknowledge (A) STOP condition (P) 1/fSCL tr tVD;DAT |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
