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Copyright © 2010 Future Technology Devices International Limited

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Document Reference No.: FT_000237

V2DIP2-48 VNC2-48 Development Module Datasheet Version 1.01

Clearance No.: FTDI# 152

Table of Contents

1

Introduction............................................................................................ 1

2

Features ................................................................................................. 3

3

Pin Out and Signal Description ............................................................ 4

3.1

Module Pin Out ....................................................................................................4

3.2

Pin Signal Description ........................................................................................6

3.3

I/O Configuration Using The Jumper Pin Header .............................................8

3.4

Default Interface I/O Pin Configuration..............................................................9

3.5

UART Interface...................................................................................................10

3.5.1

Signal Description – UART Interface.............................................................................. 10

3.6

Serial Peripheral Interface (SPI) .......................................................................11

3.6.1

Signal Description - SPI Slave ........................................................................................ 11

3.6.2

Signal Description - SPI Master ...................................................................................... 11

3.7

Parallel FIFO Interface-Asynchronous Mode ..................................................12

3.7.1

Signal Description - Parallel FIFO Interface ................................................................. 12

3.7.2

Timing Diagram – Asynchronous FIFO Mode Read and Write Cycle ..................... 13

3.8

Parallel FIFO Interface-Synchronous Mode ....................................................14

3.8.1

Timing Diagram – Synchronous FIFO Mode Read and Write Cycle ....................... 15

3.9

Debugger Interface............................................................................................17

3.9.1

Signal Description - Debugger Interface ...................................................................... 17

4

Firmware .............................................................................................. 18

4.1

Firmware Support..............................................................................................18

4.2

Available Firmware............................................................................................18

4.3

Firmware Upgrades ...........................................................................................18

5

Mechanical Dimensions ...................................................................... 19

6

Schematic Diagram ............................................................................. 20

7

Contact Information............................................................................. 21

Appendix A

– References ............................................................................................22

Appendix B

– List of Figures and Tables ....................................................................23

List of Figures...............................................................................................................23

List of Tables ................................................................................................................23

Appendix C

– Revision History ...................................................................................24