MPC950 MPC951

MOTOROLA

TIMING SOLUTIONS

BR1333 — Rev 6

6

Using the MPC951 as a Zero Delay Buffer

The external feedback option of the MPC951 clock driver

allows for its use as a zero delay buffer. By using one of the

outputs as a feedback to the PLL the propagation delay

through the device is eliminated. The PLL works to align the

output edge with the input reference edge thus producing a

near zero delay. The input reference frequency affects the

static phase offset of the PLL and thus the relative delay

between the inputs and outputs.

When used as a zero delay buffer the MPC951 will likely

be in a nested clock tree application. For these applications

the MPC951 offers a LVPECL clock input as a PLL reference.

This allows the user to use LVPECL as the primary clock

distribution device to take advantage of its far superior skew

performance. The MPC951 then can lock onto the LVPECL

reference and translate with near zero delay to low skew

LVCMOS outputs. Clock trees implemented in this fashion

will show significantly tighter skews than trees developed

from CMOS fanout buffers.

To minimize part–to–part skew the external feedback

option again should be used. The PLL in the MPC951

decouples the delay of the device from the propagation delay

variations of the internal gates. From the specification table

one sees a Tpd variation of only

±200ps, thus for multiple

devices under identical configurations the part–to–part skew

will be around 1000ps (350ps for Tpd variation plus 350ps

output–to–output skew plus 300ps for I/O jitter). By running

the devices at the highest possible input reference, this

part–to– part skew can be minimized. Higher input reference

frequencies will minimize both I/O jitter and tpd variations.

Table 1. Programmable Output Frequency Relationships

INPUTS

OUTPUTS

fsela

fselb

fselc

fseld

Qa

Qb

Qc

Qd

0

0

0

0

VCO/2

VCO/4

VCO/4

VCO/4

0

0

0

1

VCO/2

VCO/4

VCO/4

VCO/8

0

0

1

0

VCO/2

VCO/4

VCO/8

VCO/4

0

0

1

1

VCO/2

VCO/4

VCO/8

VCO/8

0

1

0

0

VCO/2

VCO/8

VCO/4

VCO/4

0

1

0

1

VCO/2

VCO/8

VCO/4

VCO/8

0

1

1

0

VCO/2

VCO/8

VCO/8

VCO/4

0

1

1

1

VCO/2

VCO/8

VCO/8

VCO/8

1

0

0

0

VCO/4

VCO/4

VCO/4

VCO/4

1

0

0

1

VCO/4

VCO/4

VCO/4

VCO/8

1

0

1

0

VCO/4

VCO/4

VCO/8

VCO/4

1

0

1

1

VCO/4

VCO/4

VCO/8

VCO/8

1

1

0

0

VCO/4

VCO/8

VCO/4

VCO/4

1

1

0

1

VCO/4

VCO/8

VCO/4

VCO/8

1

1

1

0

VCO/4

VCO/8

VCO/8

VCO/4

1

1

1

1

VCO/4

VCO/8

VCO/8

VCO/8

Table 2. Input Reference versus Output Frequency Relationships (MPC950 Only)

FB_Sel = ‘1’

FB_Sel = ‘0’

Config

fsela

fselb

fselc

fseld

Qa

Qb

Qc

Qd

Qa

Qb

Qc

Qd

1

0

0

0

0

4x

2x

2x

2x

8x

4x

4x

4x

2

0

0

0

1

4x

2x

2x

x

8x

4x

4x

2x

3

0

0

1

0

4x

2x

x

2x

8x

4x

2x

4x

4

0

0

1

1

4x

2x

x

x

8x

4x

2x

2x

5

0

1

0

0

4x

x

2x

2x

8x

2x

4x

4x

6

0

1

0

1

4x

x

2x

x

8x

2x

4x

2x

7

0

1

1

0

4x

x

x

2x

8x

2x

2x

4x

8

0

1

1

1

4x

x

x

x

8x

2x

2x

2x

9

1

0

0

0

2x

2x

2x

2x

4x

4x

4x

4x

10

1

0

0

1

2x

2x

2x

x

4x

4x

4x

2x

11

1

0

1

0

2x

2x

x

2x

4x

4x

2x

4x

12

1

0

1

1

2x

2x

x

x

4x

4x

2x

2x

13

1

1

0

0

2x

x

2x

2x

4x

2x

4x

4x

14

1

1

0

1

2x

x

2x

x

4x

2x

4x

2x

15

1

1

1

0

2x

x

x

2x

4x

2x

2x

4x

16

1

1

1

1

2x

x

x

x

4x

2x

2x

2x