PIC16F84 datasheet(33/110 Pages) MICROCHIP

33 / 110 page

 1996-2013 Microchip Technology Inc.

DS30445D-page 33

PIC16C84

7.5

Write Verify

Depending on the application, good programming prac-

tice may dictate that the value written to the Data

EEPROM should be verified (Example 7-1) to the

desired value to be written. This should be used in

applications where an EEPROM bit will be stressed

near the specification limit. The Total Endurance disk

will help determine your comfort level.

Generally the EEPROM write failure will be a bit which

was written as a '1', but reads back as a '0' (due to

leakage off the bit).

EXAMPLE 7-1:

WRITE VERIFY

BCF

STATUS, RP0 ; Bank 0

; Any code can go here

;

MOVF

EEDATA, W

; Must be in Bank 0

BSF

STATUS, RP0 ; Bank 1

READ

BSF

EECON1, RD

; YES, Read the

;

value written

BCF

STATUS, RP0 ; Bank 0

;

; Is the value written (in W reg) and

;

read (in EEDATA) the same?

;

SUBWF EEDATA, W

;

BTFSS STATUS, Z

; Is difference 0?

GOTO

WRITE_ERR

; NO, Write error

; YES, Good write

; Continue program

7.6

Protection Against Spurious Writes

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Power-up

Timer

(72

duration)

prevents

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

7.7

Data EEPROM Operation during Code

Protect

When the device is code protected, the CPU is able to

read and write unscrambled data to the Data EEPROM.

For ROM devices, there are two code protection bits

(Section 8.1). One for the ROM program memory and

one for the Data EEPROM memory.

7.8

Power Consumption Considerations

Note:

It is recommended that the EEADR<7:6>

bits be cleared. When either of these bits is

set, the maximum IDD for the device is

higher than when both are cleared. The

specification is 400

A. With EEADR<7:6>

cleared, the maximum is approximately

150

A.

TABLE 7-1

REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-on

Reset

Value on all

other resets

08h

EEDATA

EEPROM data register

xxxx xxxx

uuuu uuuu

09h

EEADR

EEPROM address register

xxxx xxxx

uuuu uuuu

88h

EECON1

—

EEIF

WRERR

WREN

---0 x000

---0 q000

89h

EECON2

EEPROM control register 2

---- ----

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not

used by Data EEPROM.

PIC16F84 Datasheet(PDF) 33 Page - Microchip Technology

PIC16F84 Datasheet(HTML) 33 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL