PIC16F84 datasheet(7/110 Pages) MICROCHIP

7 / 110 page

PIC16C84

 1996-2013 Microchip Technology Inc.

DS30445D-page 7

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16CXX uses a Harvard architecture. This

architecture has the program and data accessed from

separate memories. So the device has a program

memory bus and a data memory bus. This improves

bandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory (accesses over the same bus). Separating

program and data memory further allows instructions to

be sized differently than the 8-bit wide data word.

PIC16CXX opcodes are 14-bits wide, enabling single

word instructions. The full 14-bit wide program memory

bus fetches a 14-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions (Example 3-1). Consequently, all instructions exe-

cute in a single cycle (400 ns @ 10 MHz) except for

program branches.

The PIC16C84 addresses 1K x 14 program memory.

All program memory is internal.

PIC16CXX devices can directly or indirectly address its

registers including the program counter are mapped in

the

data

memory.

orthogonal

(symmetrical)

instruction set that makes it possible to carry out any

operation on any register using any addressing mode.

This symmetrical nature and lack of ‘special optimal

situations’ make programming with the PIC16CXX

simple yet efficient. In addition, the learning curve is

reduced significantly.

The PIC16C84 has 36 x 8 SRAM and 64 x 8 EEPROM

data memory.

PIC16F84 Datasheet(PDF) 7 Page - Microchip Technology