PIC16F84 datasheet(7/128 Pages) MICROCHIP

7 / 128 page

PIC16F8X

 1996-2013 Microchip Technology Inc.

DS30430D-page 7

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16CXX uses a Harvard architecture. This

architecture has the program and data accessed from

separate memories. So the device has a program

memory bus and a data memory bus. This improves

bandwidth over traditional von Neumann architecture

where program and data are fetched from the same

memory (accesses over the same bus). Separating

program and data memory further allows instructions to

be sized differently than the 8-bit wide data word.

PIC16CXX opcodes are 14-bits wide, enabling single

word instructions. The full 14-bit wide program memory

bus fetches a 14-bit instruction in a single cycle. A two-

stage pipeline overlaps fetch and execution of instruc-

tions (Example 3-1). Consequently, all instructions exe-

cute in a single cycle except for program branches.

The PIC16F83 and PIC16CR83 address 512 x 14 of

program memory, and the PIC16F84 and PIC16CR84

address 1K x 14 program memory. All program mem-

ory is internal.

The PIC16CXX can directly or indirectly address its

registers including the program counter are mapped in

the

data

memory.

orthogonal

(symmetrical)

instruction set makes it possible to carry out any oper-

ation on any register using any addressing mode. This

symmetrical nature and lack of ‘special optimal

situations’ make programming with the PIC16CXX

simple yet efficient. In addition, the learning curve is

reduced significantly.

PIC16F84 Datasheet(PDF) 7 Page - Microchip Technology