PIC16F87 datasheet(141/230 Pages) MICROCHIP

141 / 230 page

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DS30487D-page 141

PIC16F87/88

15.12 Watchdog Timer (WDT)

For PIC16F87/88 devices, the WDT has been modified

from previous PIC16 devices. The new WDT is code

and functionally backward compatible with previous

PIC16 WDT modules and allows the user to have a

scaler value for the WDT and TMR0 at the same time.

In addition, the WDT time-out value can be extended to

268 seconds, using the prescaler with the postscaler

when PSA is set to ‘1’.

15.12.1

WDT OSCILLATOR

The WDT derives its time base from the 31.25 kHz

INTRC. The value of WDTCON is ‘---0 1000’ on all

Resets. This gives a nominal time base of 16.38 ms,

which is compatible with the time base generated with

previous PIC16 microcontroller versions.

A new prescaler has been added to the path between

the internal RC and the multiplexors used to select the

path for the WDT. This prescaler is 16 bits and can be

programmed to divide the internal RC by 32 to 65536,

giving the time base used for the WDT a nominal range

of 1 ms to 2.097s.

15.12.2

WDT CONTROL

The WDTEN bit is located in Configuration Word 1 and

when this bit is set, the WDT runs continuously.

The SWDTEN bit is in the WDTCON register. When the

WDTEN bit in the Configuration Word 1 register is set,

the SWDTEN bit has no effect. If WDTEN is clear, then

the SWDTEN bit can be used to enable and disable the

WDT. Setting the bit will enable it and clearing the bit

will disable it.

The PSA and PS<2:0> bits (OPTION_REG register)

have the same function as in previous versions of the

PIC16 family of microcontrollers.

FIGURE 15-8:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 15-5:

PRESCALER/POSTSCALER BIT STATUS

Note:

When the OST is invoked, the WDT is held

in Reset because the WDT ripple counter

is used by the OST to perform the oscilla-

tor delay count. When the OST count has

expired, the WDT will begin counting (if

enabled).

Conditions

Prescaler

Postscaler (PSA = 1)

WDTEN = 0

Cleared

CLRWDT

command

Oscillator fail detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, ECIO

Exit Sleep + System Clock = XT, HS, LP

Cleared at end of OST

31.25 kHz

PSA

16-bit Programmable Prescaler WDT

From TMR0 Clock Source

Postscaler

PS<2:0>

PSA

WDT Time-out

To TMR0

WDTPS<3:0>

WDTEN from Configuration Word 1

SWDTEN from WDTCON

INTRC Clock

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