PIC16F87 datasheet(145/230 Pages) MICROCHIP

145 / 230 page

 2002-2013 Microchip Technology Inc.

DS30487D-page 145

PIC16F87/88

15.12.4.2

FSCM and the Watchdog Timer

When a clock failure is detected, SCS<1:0> will be

forced to ‘10’ which will reset the WDT (if enabled).

15.12.4.3

POR or Wake From Sleep

The FSCM is designed to detect oscillator failure at any

point after the device has exited Power-on Reset

(POR) or low-power Sleep mode. When the primary

system clock is EC, RC or INTRC modes, monitoring

can begin immediately following these events.

For Oscillator modes involving a crystal or resonator

(HS, LP or XT), the situation is somewhat different.

Since the oscillator may require a start-up time consid-

erably longer than the FSCM sample clock time, a false

clock failure may be detected. To prevent this, the

internal oscillator block is automatically configured as

the system clock and functions until the primary clock

is stable (the OST timer has timed out). This is identical

to Two-Speed Start-up mode. Once the primary clock is

stable, the INTRC returns to its role as the FSCM

source.

15.12.4.4

Example Fail-Safe Conditions

CONDITIONS:

The device is clocked from a crystal, crystal

operation fails and then Sleep mode is entered.

OSTS = 0

SCS = 00

OSFIF = 1

USER ACTION:

Sleep mode will exit the fail-safe condition.

Therefore, if the user code did not handle the

detected fail-safe prior to the SLEEP command,

then upon wake-up, the device will try to start

the crystal that failed and a fail-safe condition

will not be detected. Monitoring the OSTS bit will

determine if the crystal is operating. The user

should not enter Sleep mode without handling

the fail-safe condition first.

CONDITIONS:

After a POR (Power-on Reset), the device is

running in Two-Speed Start-up mode. The crys-

tal fails before the OST has expired. If a crystal

fails during the OST period, a fail-safe condition

will not be detected (OSFIF will not get set).

OSTS = 0

SCS = 00

OSFIF = 0

USER ACTION:

Check the OSTS bit. If it’s clear and the OST

should have expired at this point, then the user

can assume the crystal has failed. The user

should change the SCS bit to cause a clock

switch which will also release the 10-bit ripple

counter for WDT operation (if enabled).

CONDITIONS:

The device is clocked from a crystal during

normal operation and it fails.

OSTS = 0

SCS = 00

OSFIF = 1

USER ACTION:

Clear the OSFIF bit. Configure the SCS bits for

a clock switch and the fail-safe condition will be

cleared. Later, if the user decides to, the crystal

can be retried for operation. If this is done, the

OSTS bit should be monitored to determine if

the crystal operates.

15.13 Power-Down Mode (Sleep)

Power-Down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (STATUS<3>) is cleared, the

TO (STATUS<4>) bit is set and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low or high-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D and disable external clocks. Pull all I/O pins

that are high-impedance inputs, high or low externally,

to avoid switching currents caused by floating inputs.

The T0CKI input should also be at VDD or VSS for low-

est current consumption. The contribution from on-chip

pull-ups on PORTB should also be considered.

The MCLR pin must be at a logic high level (VIHMC).

Note:

The same logic that prevents false oscilla-

tor failure interrupts on port or wake from

Sleep, will also prevent the detection of

the oscillator’s failure to start at all follow-

ing these events. This can be avoided by

monitoring the OSTS bit and using a

timing routine to determine if the oscillator

is taking too long to start. Even so, no

oscillator failure interrupt will be flagged.

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