PIC16F87 datasheet(146/230 Pages) MICROCHIP

146 / 230 page

PIC16F87/88

DS30487D-page 146

 2002-2013 Microchip Technology Inc.

15.13.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

External Reset input on MCLR pin.

Watchdog Timer wake-up (if WDT was enabled).

Interrupt from INT pin, RB port change or a

peripheral interrupt.

External MCLR Reset will cause a device Reset. All

other events are considered a continuation of program

execution and cause a “wake-up”. The TO and PD bits

in the STATUS register can be used to determine the

cause of the device Reset. The PD bit, which is set on

power-up, is cleared when Sleep is invoked. The TO bit

is cleared if a WDT time-out occurred and caused

wake-up.

The following peripheral interrupts can wake the device

from Sleep:

TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

CCP Capture mode interrupt.

Special event trigger (Timer1 in Asynchronous

mode using an external clock).

SSP (Start/Stop) bit detect interrupt.

SSP transmit or receive in Slave mode (SPI/I2C).

A/D conversion (when A/D clock source is RC).

EEPROM write operation completion.

Comparator output changes state.

AUSART RX or TX (Synchronous Slave mode).

Other peripherals cannot generate interrupts, since

during Sleep, no on-chip clocks are present.

When the SLEEP instruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the instruction after the SLEEP instruction. If the GIE bit

is set (enabled), the device executes the instruction

after the SLEEP instruction and then branches to the

interrupt address (0004h). In cases where the execu-

tion of the instruction following SLEEP is not desirable,

the user should have a NOP after the SLEEP instruction.

15.13.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEP

instruction, the SLEEP instruction will

complete as a NOP. Therefore, the WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

• If the interrupt occurs during or after the

execution of a SLEEP instruction, the device will

immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT prescaler

and postscaler (if enabled) will be cleared, the TO

bit will be set and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT instruction

should be executed before a SLEEP instruction.

FIGURE 15-12:

WAKE-UP FROM SLEEP THROUGH INTERRUPT(1)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO(4)

INT pin

INT0IF Flag

(INTCON<1>)

GIE bit(3)

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2

0004h

0005h

Dummy Cycle

TOST(2)

PC + 2

Note

XT, HS or LP Oscillator mode assumed.

TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Oscillator mode.

GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine.

If GIE = 0, execution will continue in-line.

CLKO is not available in these oscillator modes, but shown here for timing reference.

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