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PIC16F87 Datasheet(PDF) 187 Page - Microchip Technology |
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PIC16F87 Datasheet(HTML) 187 Page - Microchip Technology |
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187 / 230 page ![]() 2002-2013 Microchip Technology Inc. DS30487D-page 187 PIC16F87/88 FIGURE 18-16: AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TABLE 18-11: AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS FIGURE 18-17: AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TABLE 18-12: AUSART SYNCHRONOUS RECEIVE REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions 120 TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid PIC16F87/88 — — 80 ns PIC16LF87/88 — — 100 ns 121 Tckrf Clock Out Rise Time and Fall Time (Master mode) PIC16F87/88 — — 45 ns PIC16LF87/88 — — 50 ns 122 Tdtrf Data Out Rise Time and Fall Time PIC16F87/88 — — 45 ns PIC16LF87/88 — — 50 ns † Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance only and are not tested. Param No. Sym Characteristic Min Typ† Max Units Conditions 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data Setup before CK (DT setup time) 15 — — ns 126 TckL2dtl Data Hold after CK (DT hold time) 15 — — ns † Data in “Typ” column is at 5V, 25 C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Refer to Figure 18-3 for load conditions. 121 121 122 RB5/SS/TX/CK RB2/SDO/RX/DT pin pin 120 Note: Refer to Figure 18-3 for load conditions. 125 126 RB5/SS/TX/CK RB2/SDO/RX/DT pin pin |
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