PIC18F23K22 datasheet(39/42 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

Advance Information

DS41398B-page 39

PIC18(L)F2XK22/4XK22

P14

TVALID Data Out Valid from PGC



—

P15

THLD4

Input data hold time from MCLR



400

—

s

P16

TDLY8

Delay between Last PGC

 and MCLR/VPP/RE3 

0—

P17

THLD3MCLR/VPP/RE3

to VDD 

—

100

P18

TKEY1

Delay from First MCLR

to first PGC for Key Sequence

on PGD

1—

P19

THIZ

Delay from PGC

to PGD High-Z

310

P20

TKEY2

Delay from Last PGC

for Key Sequence on PGD to

Second MCLR



—

Standard Operating Conditions

Operating Temperature: 25

C is recommended

Param

No.

Sym.

Characteristic

Min.

Max.

Units

Conditions

Note 1:

Do not allow excess time when transitioning MCLR between VIL and VIHH; this can cause spurious program executions

to occur. The maximum transition time is:

1 TCY + TPWRT (if enabled) + 1024 TOSC (for LP, HS, HS/PLL and XT modes only) + 2 ms (for HS/PLL mode only) + 1.5

s (for EC mode only) where TCY is the instruction cycle time, TPWRT is the Power-up Timer period and TOSC is the

oscillator period. For specific values, refer to the Electrical Characteristics section of the device data sheet for the

particular device.

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