TCN75

DS21490D-page 12

 2001-2012 Microchip Technology Inc.

FIGURE 5-1:

Timing Diagrams

1

1

Start

by

Master

Ack

by

TCN75

Address Byte

(a) Typical 2-Byte Read From Preset Pointer Location Such as Temp, TOS, THYST

(b) Typical Pointer Set Followed by Immediate Read for 2-Byte Register Such as Temp, TOS, THYST

Ack

by

Master

Most Significant Data Byte

Stop

Cond

by

Master

No Ack

by

Master

Least Significant Data Byte

D7 D6 D5 D4 D3 D2 D1 D0

00

1

91

99

1

1

Start

by

Master

Ack

by

TCN75

Address Byte

Ack

by

TCN75

Pointer Byte

00

000

0

D1 D0

. . . . .

. . . . .

1

A2 A1 A0 R/W

00

1

99

1

1

Start

by

Master

Ack

by

TCN75T

Address Byte

(c) Typical 1-Byte Read From Configuration Register with Preset Pointer

Data Byte

Stop

Cond

by

Master

No Ack

by

Master

D7 D6 D5 D4 D3 D2 D1 D0

1

A2 A1 A0 R/W

00

1

99

1

1

Repeat

Start

by

Master

Ack

by

TCN75

Address Byte

Ack

by

Master

Most Significant Data Byte

Stop

Cond

by

Master

No Ack

by

Master

Least Significant Data Byte

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

1

A2 A1 A0 R/W

00

1

91

99