MCP3911 datasheet(19/72 Pages) MICROCHIP

19 / 72 page

DS22286A-page 19

MCP3911

3.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

3.1

Master Reset (RESET)

This pin is active low and places the entire chip in a

reset state when active.

When RESET=0, all registers are reset to their default

value, no communication can take place, and no clock

is distributed inside the part, except in the input struc-

ture if MCLK is applied (if idle, then no clock is distrib-

uted). This state is equivalent to a POR state.

Since the default state of the ADCs is on, the analog

power consumption, when RESET=0, is equivalent to

when RESET=1. Only the digital power consumption is

largely reduced because this current consumption is

essentially dynamic and is reduced drastically when

there is no clock running.

All the analog biases are enabled during a reset so that

the part is fully operational just after a RESET rising

edge, if the MCLK is applied during the rising edge. If

not applied, there is a small time after RESET where

the conversion may not be accurate corresponding to

the startup of the charge pump of the input structure.

This input is Schmitt triggered.

3.2

Digital VDD (DVDD)

DVDD is the power supply pin for the digital circuitry

within the MCP3911. This pin requires appropriate

bypass capacitors and should be maintained between

2.7V and 3.6V for specified operation.

3.3

Analog VDD (AVDD)

AVDD is the power supply pin for the analog circuitry

within the MCP3911. This pin requires appropriate

bypass capacitors and should be maintained to 2.7V

and 3.6V for specified operation.

3.4

ADC Differential Analog inputs

(CHn+/CHn-)

CH0- and CH0+, and CH1- and CH1+, are the two

fully-differential

analog

voltage

inputs

for

the

Delta-Sigma ADCs.

Pin No.

SSOP

Pin No.

QFN

Symbol

Function

RESET

Master Reset Logic Input Pin

219

DVDD

Digital Power Supply Pin

320

AVDD

Analog Power Supply Pin

CH0+

Non-Inverting Analog Input Pin for Channel 0

CH0-

Inverting Analog Input Pin for Channel 0

CH1-

Inverting Analog Input Pin for Channel 1

CH1+

Non-Inverting Analog Input Pin for Channel 1

AGND

Analog Ground Pin, Return Path for internal analog circuitry

REFIN+/OUT

Non-Inverting Voltage Reference Input and Internal Reference Output Pin

REFIN-

Inverting Voltage Reference Input Pin

DGND

Digital Ground Pin, Return Path for internal digital circuitry

MDAT1

Modulator Data Output Pin for Channel 1

MDAT0

Modulator Data Output Pin for Channel 0

Data Ready Signal Output Pin

OSC1/CLKI

Oscillator Crystal Connection Pin or External Clock Input Pin

OSC2

Oscillator Crystal Connection Pin

Serial Interface Chip Select Pin

SCK

Serial Interface Clock Input Pin

SDO

Serial Interface Data Input Pin

SDI

Serial Interface Data Input Pin

Exposed Thermal Pad. Must be connected to AGND.

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