0.1

1.0

10.0

100.0

1000.0

SWITCHING FREQUENCY (kHz)

0.001

0.010

0.100

1.000

To Hi-Side FET

To Low-Side FET

Single Layer

Option

Multi Layer

Option

Recommended Layout for Driver IC and

Passives

VSS

LO

LI

SO

PowerPAD-8

HI

VDD

HB

HO

HS

LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C

SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013

www.ti.com

Power Dissipation Considerations

The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate

voltage (VDD) and can be roughly calculated as:

2

(1)

There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and

HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load

capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the

power losses driving the output loads and agrees well with the above equation.Equation 1 This plot can be used

to approximate the power losses due to the gate drivers.

Figure 25. Gate Driver Power Dissipation (LO + HO)

12

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