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DP83848JSQ Datasheet(PDF) 66 Page - Texas Instruments |
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DP83848JSQ Datasheet(HTML) 66 Page - Texas Instruments |
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66 / 80 page ![]() 65 www.national.com 8.2.7 100BASE-TX Transmit Packet Deassertion Timing Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser- tion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode. Parameter Description Notes Min Typ Max Units T2.7.1 TX_CLK to PMD Output Pair Deassertion 100 Mb/s Normal mode 6 bits TX_CLK TXD TX_EN PMD Output Pair (T/R) DATA IDLE T2.7.1 (T/R) DATA IDLE |
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