Signal driven by Master.

For reference only.

Signal not driven; pull-down only.

SA3

SA2

SA1

SA0

1

P

Data

SDATA

SCLK

Slave Address

0

D1

D0

D2

D5

D4

D3

D6

SSC

Bus

Park

Parity

t0

t3

t2

t1

Trigger is programmed. VSET and

SMPS_CFG loaded from shadow

registers. LM3263 initializes and

powers up internal circuit blocks.

Transmit Slot Boundary. DC-DC

output settled (95%).

VBATT applied, VIO = 0V.

LM3263 in Shutdown.

t4

VIO

RFFE write

SMPS_CFG= auto PFM

(Reg 01h = 20h)

SDATA

VOUT

3.4V

0V

t0

t4

t3

t2

t1

VIO applied.150ns later

LM3263 is in Low Power, and

RFFE configuration writes may

occur.

DC-DC is active in normal mode.

VBATT

5 Ps (min)

25 Ps max

50 Ps max

RFFE write

(Reg 03h = E3h)

APT

Active

Shutdown

Low Power

Initialization

SW

RFFE write

PM_TRIG

(Reg 1Ch = 02h)

LM3263

www.ti.com

SNVS837 – JUNE 2013

Figure 22. Triggered Startup Sequence

RFFE Interface

The Digital Control Serial Bus Interface provides MIPI RF Front-End Control Interface compatible access to the

programmable functions and registers on the device. The LM3263 uses a three-pin digital interface; two for

bidirectional communications between the IC’s connected to the bus, along with an interface voltage reference

VIO that also acts as asynchronous enable and reset. When VIO voltage supply is applied to the Bus, it enables

the Slave interface and resets the user-defined Slave registers to the default settings. The LM3263 can be set to

shutdown mode via the asynchronous VIO signal or low-power mode by setting the appropriate register via Serial

Bus Interface. The two communication lines are serial data (SDATA), and clock (SCLK). SCLK and SDATA must

be held low until VIO is present. The LM3263 connects as slave on a single-master Serial Bus Interface.

The SDATA signal is bidirectional, driven by the Master or a Slave. Data is written on the rising edge (transition

from logical level zero to logical level one) of the SCLK signal by both Master and Slaves. Master and Slave both

read the data on the falling edge (transition from logical level one to logical level zero) of the SCLK signal. A

logic-low level applied to VIO signal powers off the digital interface.

Supported Command Sequences

Figure 23. Register 0 Write

Copyright © 2013, Texas Instruments Incorporated

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