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FV80503CSM66166 Datasheet(PDF) 49 Page - Intel Corporation |
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FV80503CSM66166 Datasheet(HTML) 49 Page - Intel Corporation |
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49 / 62 page ![]() Low-Power Embedded Pentium® Processor with MMX™ Technology Datasheet 49 t40 Reset Configuration Signals (INIT, FLUSH#) Setup Time 5.0 ns 17 (7, 8, 10) t41 Reset Configuration Signals (INIT, FLUSH#) Hold Time 1.0 ns 17 (9) t42a Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. 2.0 CLKs 17 To RESET falling edge, (8) t42b Reset Configuration Signals (INIT, FLUSH#) Setup Time, Async. 2.0 CLKs 17 To RESET falling edge t43a BF2–BF0 Setup Time 1.0 mS 17 To RESET falling edge, (10) t43b BF2–BF0 Hold Time 2.0 CLKs 17 To RESET falling edge, (12) t43c APICEN, BE4# Setup Time 2.0 CLKs 17 To RESET falling edge t43d APICEN, BE4# Hold Time 2.0 CLKs 17 To RESET falling edge t44 TCK Frequency — 16.0 MHz t45 TCK Period 62.5 ns 13 t46 TCK High Time 25.0 ns 13 @VCC3 –0.7 V, (2) t47 TCK Low Time 25.0 ns 13 @0.5 V, (2) t48 TCK Fall Time 5.0 ns 13 VCC3 –0.7 V to 0.5 V (2, 13, 14) t49 TCK Rise Time 5.0 ns 13 0.5 V to VCC3 –0.7 V, (2, 13, 14) t50 TRST# Pulse Width 40.0 ns 19 Asynchronous, (2) t51 TDI, TMS Setup Time 5.0 ns 19 (15) t52 TDI, TMS Hold Time 13.0 ns 19 (15) t53 TDO Valid Delay 3.0 20.0 ns 19 (13) t54 TDO Float Delay 25.0 ns 19 (2, 13) t55 All Non-Test Outputs Valid Delay 3.0 20.0 ns 19 (13, 16, 17) t56 All Non-Test Outputs Float Delay 25.0 ns 19 (2, 13, 16, 17) t57 All Non-Test Inputs Setup Time 5.0 ns 19 (15, 16, 17) t58 All Non-Test Inputs Hold Time 13.0 ns 19 (15, 16, 17) Table 23. Low-Power Embedded Pentium® Processor with MMX™ Technology AC Specifications (Sheet 3 of 3) (See Table 18 for VCC and TCASE assumptions.) Symbol Parameter Min Max Unit Figure Notes (see Table 25) |
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