ADDI7100

Rev. C | Page 6 of 20

CCD

SIGNAL

(CCDIN)

EFFECTIVE PIXELS

CLPOB

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

DUMMY PIXELS

EFFECTIVE PIXELS

PBLK

NOTES

1. CLPOB AND PBLK SHOULD BE ALIGNED WITH THE CCD SIGNAL INPUT (CCDIN).

CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.

2. PBLK SIGNAL IS OPTIONAL. KEEP THE PBLK PIN IN THE INACTIVE STATE IF NOT USED.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS FIFTEEN DATACLK CYCLES.

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA

DUMMY BLACK

EFFECTIVE DATA

ACTIVE

ACTIVE

Figure 4. Typical Clamp Timing (Default Polarity Settings)