IR3897MPBF datasheet(4/47 Pages) IRF

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JANUARY 18, 2013 |DATA SHEET | Rev 3.5

IR3897

4A Highly Integrated SupIRBuck

Single‐Input Voltage, Synchronous Buck Regulator

PD‐97663

PIN DESCRIPTIONS

PIN #

PIN NAME

PIN DESCRIPTION

Inverting input to the error amplifier. This pin is connected directly to the output

of the regulator via resistor divider to set the output voltage and provide

feedback to the error amplifier.

Vref

Internal reference voltage , it can be used for margining operation also. In

normal and sequencing mode operation, a 100pF ceramic capacitor is

recommended between this pin and Gnd. In tracking mode operation, Vref

should be tied to Gnd.

Comp

Output of error amplifier. An external resistor and capacitor network is typically

connected from this pin to Fb to provide loop compensation.

Gnd

Signal ground for internal reference and control circuitry.

Rt/Sync

Multi‐function pin to set switching frequency. Use an external resistor from this

pin to Gnd to set the free‐running switching frequency. Or use an external clock

signal to connect to this pin through a diode, the device’s switching frequency is

synchronized with the external clock.

S_Ctrl

Soft start/stop control. A high logic input enables the device to go into the

internal soft start; a low logic input enables the output soft discharged. Pull this

pin high if this function is not used.

PGood

Power Good status pin. Output is open drain. Connect a pull up resistor (49.9k)

from this pin to the voltage lower than or equal to the Vcc.

Vsns

Sense pin for over‐voltage protection and PGood. It is optional to tie this pin to

FB pin directly instead of using a resistor divider from Vout.

Vin

Input voltage for Internal LDO. A 1.0µF capacitor should be connected between

this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin

should be shorted to Vcc/LDO_out pin.

Vcc/LDO_Out

Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum

2.2µF cap from this pin to PGnd.

PGnd

Power Ground. This pin serves as a separated ground for the MOSFET drivers

and should be connected to the system’s power ground plane.

Switch node. This pin is connected to the output inductor.

PVin

Input voltage for power stage.

Boot

Supply voltage for high side driver, a 100nF capacitor should be connected

between this pin and SW pin.

Enable

Enable pin to turn on and off the device, if this pin is connected to PVin pin

through a resistor divider, input voltage UVLO can be implemented.

Input to error amplifier for tracking purposes. In the normal operation, it is left

floating and no external capacitor is required. In the sequencing or the tracking

mode operation, an external signal can be applied as the reference.

Gnd

Signal ground for internal reference and control circuitry.

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