( )

(

)

IN

OUT

OUT

LOAD LL

X

IN

SW

V

V

V

1

I

2

L

V

f

-

=

´

´

´

PWM

Comparator

Control

Logic

and

Driver

22

VIN

VSNS

G

26

VREF

2.0 V

–

+

R1

R2

TPS51363

ESR

SW

21

SLEW

C1

+

–

25

REFIN

+

UDG-13014

PGND

CSP

CSN

LC

0

OUT

OUT

1

1

f

f

10

2

L

C

=

£

´

p ´

´

TPS51363

SLUSBB5A – FEBRUARY 2013 – REVISED JUNE 2013

www.ti.com

The device operates at two distinct switching frequencies, 400 kHz and 800 kHz. The switching frequency is

configured by MODE pin for this converter operation (see Table 3). For stable operation of the buck converter, it

Table 3).

Table 3. Mode and Recommended Frequency Settings

FREQUENCY (kHz)

MODE

MIN

MAX

GND

100

133

400

FLOAT

200

267

800

Given the range of the recommended unity gain frequency, the power stage design is flexible, as long as the

following equation is satisfied.

(2)

Operating in D-CAP2 mode, the overall loop response is dominated by the internal phase compensation network.

The compensation network is designed to have two identical zeros at 4 kHz (400-kHz operation) and 8 kHz (800-

kHz operation) in the frequency domain, which serves the purpose of splitting the LC double pole into one low

frequency pole (same as the L-C double pole) and one high-frequency pole (greater than the unity gain

crossover frequency).

Figure 30. Simplified Architecture Illustrating DCAP2 Mode

Light-Load Operation

The mandatory light load operation for TPS51363 is referred to as auto skip. In auto-skip mode, the control logic

automatically reduces its switching frequency to improve light load efficiency. To achieve this intelligence, a zero

crossing detection comparator is used to prevent negative inductor current by turning off the low side FET when

the SW crossing zero is detected. The equation below shows the boundary load condition of this skip mode and

continuous conduction operation.

(3)

16

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