LPC81XM_13 datasheet(35/71 Pages) NXP

35 / 71 page

LPC81xM

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Product data sheet

Rev. 3 — 29 July 2013

35 of 71

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[6]

BOD disabled.

[7]

All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system

configuration block.

[8]

IRC enabled; system oscillator disabled; system PLL enabled.

[9]

IRC disabled; system oscillator enabled; system PLL enabled.

[10] All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0x0000 18FF.

[11] WAKEUP pin pulled HIGH externally.

[12] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles.

[13] Including voltage on outputs in tri-state mode.

[14] VDD supply voltage must be present.

[15] 3-state outputs go into tri-state mode in Deep power-down mode.

[16] Allowed as long as the current limit does not exceed the maximum current allowed by the device.

[17] Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 7.

[18] To VSS.

Fig 12. Pin input/output current measurement

LPC81XM Datasheet(PDF) 35 Page - NXP Semiconductors