CN-0294

Circuit Note

Rev. 0 | Page 4 of 5

Phase Noise and Jitter Measurement

1. Repeat Step 1 to Step 4 from the Logic Level Measurement

section.

2. Terminate the unused CLK2 output of the

ADCLK948/PCBZ with a 50 Ω load (see Figure 5).

3. Connect the CLK2 output via a SMA cable to the signal

source analyzer (see Figure 5).

4. Measure the jitter performance of the signal.

Figure 6 shows the phase noise at the output of the ADF4351,

and the rms jitter is 325.7 fs. Figure 7 shows the phase noise at

the ADCLK948 output. The rms jitter is 330.4 fs.

The additive jitter of the ADCLK948 can be calculated as

the ADCLK948 data sheet is 75 fs rms.

SPECTRUM

ANALYZER

(R&S FSUP26)

POWER

SUPPLY

50Ω

TERM

RFOUTA+

RFOUTA−

PC

USB

COM

3.3V

ADF4351

EVALUATION BOARD

(EVAL-ADF4351EB1Z)

T7

ADCLK948/PCBZ

EVALUATION BOARD

J4

J2

CLK0

OUT2

CLK0

OUT2

Figure 5. ADF4351 Phase Noise and Jitter Measurement Setup

R&S FSUP 26 Signal Source Analyzer

LOCKED

Settings

Residual Noise [T1 w/o spurs]

Phase Detector +20 dB

Signal Frequency:

999.999524 MHz

Int PHN (1.0 k .. 30.0 M) –56.8 dBc

Signal Level:

–3.86 dBm

Residual PM

0.117 °

Cross Corr Mode

Harmonic 1

Residual FM

2.939 kHz

Internal Ref Tuned

Internal Phase Det

RMS Jitter

0.3257 ps

Phase Noise [dBc/Hz]

Marker 1 [T1]

Marker 2 [T1]

Marker 3 [T1]

Marker 4 [T1]

RF Atten

5 dB

1 kHz

10 kHz

100 kHz

1 MHz

Top –70 dBc/Hz

–101.53 dBc/Hz

–104.91 dBc/Hz

–113.11 dBc/Hz

–142.41 dBc/Hz

–160

–150

–140

–130

–120

–110

–100

–90

–80

10kHz

100kHz

1MHz

10MHz

1kHz

30MHz

–160

–150

–140

–130

–120

–110

–100

–90

–80

Spur Power (dBc)

LoopBW 300Hz

2 CLRWR

A

1 CLRWR

SMTH 1%

SPR OFF

TH 0dB

FREQUENCY OFFSET

1

2

3

4

Figure 6. ADF4351 Output Phase Noise Measurement Showing 325.7 fs rms Jitter