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DSPIC33FJ32GP302TH/SP Datasheet(PDF) 83 Page - Microchip Technology |
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DSPIC33FJ32GP302TH/SP Datasheet(HTML) 83 Page - Microchip Technology |
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83 / 403 page  2009 Microchip Technology Inc. Preliminary DS70292D-page 83 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 FIGURE 6-2: SYSTEM RESET TIMING Reset Run Device Status VDD VPOR Vbor VBOR POR Reset BOR Reset SYSRST TPWRT TPOR TBOR Oscillator Clock TOSCD TOST TLOCK Time FSCM TFSCM 1 2 3 4 5 6 Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay TPOR has elapsed. 2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable. 3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles. 4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information. 5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay TFSCM elapsed. |
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