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DSPIC33FJ32GP302TH/SP Datasheet(PDF) 93 Page - Microchip Technology |
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DSPIC33FJ32GP302TH/SP Datasheet(HTML) 93 Page - Microchip Technology |
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93 / 403 page  2009 Microchip Technology Inc. Preliminary DS70292D-page 93 dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 REGISTER 7-2: CORCON: CORE CONTROL REGISTER(1) U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0 — — — US EDT DL<2:0> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF bit 7 bit 0 Legend: C = Clear only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set 0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. |
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