DSPIC33FJ32GP302THSLASHSP datasheet(131/403 Pages) MICROCHIP

131 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 131

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

8.1

DMAC Registers

Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)

contains the following registers:

• A 16-bit DMA Channel Control register

(DMAxCON)

• A 16-bit DMA Channel IRQ Select register

(DMAxREQ)

• A 16-bit DMA RAM Primary Start Address register

(DMAxSTA)

• A 16-bit DMA RAM Secondary Start Address

• A 16-bit DMA Peripheral Address register

(DMAxPAD)

• A 10-bit DMA Transfer Count register (DMAxCNT)

An additional pair of status registers, DMACS0 and

DMACS1, are common to all DMAC channels.

DMACS0 contains the DMA RAM and SFR write colli-

sion flags, XWCOLx and PWCOLx, respectively.

DMACS1 indicates DMA channel and Ping-Pong mode

status.

The

DMAxCON,

DMAxREQ,

DMAxPAD

and

DMAxCNT are all conventional read/write registers.

Reads of DMAxSTA or DMAxSTB reads the contents

of the DMA RAM Address register. Writes to DMAx-

STA or DMAxSTB write to the registers. This allows

the user to determine the DMA buffer pointer value

(address) at any time.

The interrupt flags (DMAxIF) are located in an IFSx

interrupt enable control bits (DMAxIE) are located in

an IECx register in the interrupt controller, and the cor-

responding interrupt priority control bits (DMAxIP) are

located in an IPCx register in the interrupt controller.

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 131 Page - Microchip Technology