PIC18F1220ESLASHPQTP datasheet(36/308 Pages) MICROCHIP

36 / 308 page

PIC18F1220/1320

DS39605F-page 34

4.1

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected. To take advantage of the POR

circuitry, just tie the MCLR pin through a resistor (1k to

10 k

Ω) to VDD. This will eliminate external RC compo-

nents usually needed to create a Power-on Reset

delay. A minimum rise rate for VDD is specified

(parameter D004). For a slow rise time, see Figure 4-2.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

FIGURE 4-2:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

4.2

Power-up Timer (PWRT)

The Power-up Timer (PWRT) of the PIC18F1220/1320 is

an 11-bit counter, which uses the INTRC source as the

clock input. This yields a count of 2048 x 32

μs= 65.6 ms.

While the PWRT is counting, the device is held in Reset.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameter 33 for details.

The PWRT is enabled by clearing configuration bit,

PWRTEN.

4.3

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter 33). This ensures that

the crystal oscillator or resonator has started and

stabilized.

The OST time-out is invoked only for XT, LP, HS and

HSPLL modes and only on Power-on Reset, or on exit

from most low-power modes.

4.4

PLL Lock Time-out

With the PLL enabled in its PLL mode, the time-out

sequence following a Power-on Reset is slightly

different from other oscillator modes. A portion of the

Power-up Timer is used to provide a fixed time-out that

is sufficient for the PLL to lock to the main oscillator fre-

quency. This PLL lock time-out (TPLL) is typically 2 ms

and follows the Oscillator Start-up Time-out.

4.5

Brown-out Reset (BOR)

A configuration bit, BOR, can disable (if clear/

programmed), or enable (if set) the Brown-out Reset

circuitry. If VDD falls below VBOR (parameter D005) for

greater than TBOR (parameter 35), the brown-out situa-

tion will reset the chip. A Reset may not occur if VDD

falls below VBOR for less than TBOR. The chip will

remain in Brown-out Reset until VDD rises above VBOR.

If the Power-up Timer is enabled, it will be invoked after

VDD rises above VBOR; it then will keep the chip in

Reset

for

additional

time

delay,

TPWRT

(parameter 33). If VDD drops below VBOR while the

Power-up Timer is running, the chip will go back into a

Brown-out Reset and the Power-up Timer will be initial-

ized. Once VDD rises above VBOR, the Power-up Timer

will execute the additional time delay. Enabling BOR

Reset does not automatically enable the PWRT.

4.6

Time-out Sequence

On power-up, the time-out sequence is as follows:

First, after the POR pulse has cleared, PWRT time-out

is invoked (if enabled). Then, the OST is activated. The

total time-out will vary based on oscillator configuration

and the status of the PWRT. For example, in RC mode

with the PWRT disabled, there will be no time-out at all.

Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and

Figure 4-7 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, all time-outs will expire. Bring-

ing MCLR high will begin execution immediately

(Figure 4-5). This is useful for testing purposes or to

synchronize more than one PIC18FXXXX device

operating in parallel.

Table 4-2 shows the Reset conditions for some Special

Function Registers, while Table 4-3 shows the Reset

conditions for all the registers.

Note

1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 k

Ω is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1

≥ 1 kΩ will limit any current flowing into

MCLR from external capacitor C, in the event

of MCLR/VPP pin breakdown due to Electro-

static

Discharge

(ESD)

Electrical

Overstress (EOS).

VDD

MCLR

PIC18FXXXX

VDD

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