PIC18F1220ESLASHPQTP datasheet(18/308 Pages) MICROCHIP

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PIC18F1220/1320

DS39605F-page 16

2.7.1

OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 2-2) controls several

aspects of the system clock’s operation, both in full

power operation and in power managed modes.

The System Clock Select bits, SCS1:SCS0, select the

clock source that is used when the device is operating in

power managed modes. The available clock sources are

the primary clock (defined in Configuration Register 1H),

the secondary clock (Timer1 oscillator) and the internal

oscillator block. The clock selection has no effect until a

SLEEP

instruction is executed and the device enters a

power managed mode of operation. The SCS bits are

cleared on all forms of Reset.

The Internal Oscillator Select bits, IRCF2:IRCF0, select

the frequency output of the internal oscillator block that

is used to drive the system clock. The choices are the

INTRC source, the INTOSC source (8 MHz), or one of

the

six

frequencies

derived

from

the

INTOSC

postscaler (125 kHz to 4 MHz). If the internal oscillator

block is supplying the system clock, changing the

states of these bits will have an immediate change on

the internal oscillator’s output.

The OSTS, IOFS and T1RUN bits indicate which clock

source is currently providing the system clock. The

OSTS indicates that the Oscillator Start-up Timer has

timed out and the primary clock is providing the system

clock in Primary Clock modes. The IOFS bit indicates

when the internal oscillator block has stabilized and is

providing the system clock in RC Clock modes or

during

Two-Speed

Start-ups.

The

T1RUN

bit

(T1CON<6>) indicates when the Timer1 oscillator is

providing the system clock in Secondary Clock modes.

In power managed modes, only one of these three bits

will be set at any time. If none of these bits are set, the

INTRC is providing the system clock, or the internal

oscillator block has just started and is not yet stable.

The IDLEN bit controls the selective shutdown of the

controller’s CPU in power managed modes. The uses

of these bits are discussed in more detail in

Section 3.0 “Power Managed Modes”.

FIGURE 2-8:

PIC18F1220/1320 CLOCK DIAGRAM

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator

is not enabled, then any attempt to select

secondary

clock

source

when

executing a SLEEP instruction will be

ignored.

2: It is recommended that the Timer1 oscil-

lator be operating and stable before exe-

cuting the SLEEP instruction or a very

long delay may occur while the Timer1

oscillator starts.

PIC18F1220/1320

4 x PLL

CONFIG1H <3:0>

Secondary Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for Other Modules

OSC1

OSC2

Sleep

Primary Oscillator

HSPLL

LP, XT, HS, RC, EC

T1OSC

CPU

Peripherals

IDLEN

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON<6:4>

111

110

101

100

011

010

001

000

31 kHz

INTRC

Source

Internal

Oscillator

Block

WDT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON<6:4>

Clock

Control

OSCCON<1:0>

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