EPC2TC32 datasheet(15/26 Pages) ALTERA

15 / 26 page

IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing

Page 15

Configuration Devices for SRAM-Based LUT Devices

January 2012

Altera Corporation

Figure 4 shows the timing requirements for the JTAG signals.

Table 7 lists the timing parameters and values for configuration devices.

Figure 4. EPC2 Device JTAG Waveforms

Table 7. JTAG Timing Parameters and Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK

clock period

100

—

tJCH

TCK

clock high time

—

tJCL

TCK

clock low time

—

tJPSU

JTAG port setup time

—

tJPH

JTAG port hold time

—

tJPCO

JTAG port clock to output

—

tJPZX

JTAG port high impedance to valid output

—

tJPXZ

JTAG port valid output to high impedance

—

tJSSU

Capture register setup time

—

tJSH

Capture register hold time

—

tJSCO

Update register clock to output

—

tJSZX

Update register high impedance to valid output

—

tJSXZ

Update register valid output to high impedance

—

TDO

TCK

tJPZX

tJPCO

tJPH

tJPXZ

tJCP

tJPSU

tJCL

tJCH

TDI

TMS

Signal

to be

Captured

Signal

to be

Driven

tJSZX

tJSSU

tJSH

tJSCO

tJSXZ

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