PAL16R4 datasheet(14/27 Pages) TI

14 / 27 page

TIBPAL16R4-25C, TIBPAL16R6-25C, TIBPAL16R8-25C

TIBPAL16R4-30M, TIBPAL16R6-30M, TIBPAL16R8-30M

LOW-POWER HIGH-PERFORMANCE

IMPACT ™ PAL® CIRCUITS

SRPS059A FEBRUARY 1984 − REVISED DECEMBER 2010

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

power-up reset (see Figure 2)

Following power up, all registers are set high. This feature provides extra flexibility to the system designer and

is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important

that the rise of VCC be monotonic. Following power-up reset, a low-to-high clock transition must not occur until

all applicable input and feedback setup times are met.

1.5 V

tsu‡

tpd†

VIL

VIH

5 V

VCC

Active-Low

Registered Output

CLK

4 V

VOH

VOL

1.5 V

(600 ns TYP, 1000 ns MAX)

1.5 V

† This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.

‡ This is the setup time for input or feedback.

Figure 2. Power-Up Reset Waveforms

PAL16R4 Datasheet(PDF) 14 Page - Texas Instruments