AD5317 datasheet(16/24 Pages) AD

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AD5305/AD5315/AD5325

Rev. G | Page 16 of 24

SERIAL INTERFACE

The AD5305/AD5315/AD5325 are controlled via an I2C

compatible serial bus. The DACs are connected to this bus as

slave devices (that is, no clock is generated by the AD5305/

AD5315/AD5325 DACs). This interface is SMBus compatible

at VDD < 3.6 V.

The AD5305/AD5315/AD5325 have a 7-bit slave address. The

6 MSB are 000110 and the LSB is determined by the state of the

A0 pin. The facility to make hardwired changes to A0 allows the

user to use up to two of these devices on one bus. The 2-wire

serial bus protocol operates as follows:

The master initiates data transfer by establishing a start

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high. The following byte is

the address byte, which consists of the 7-bit slave address

followed by an R/W bit (this bit determines whether data is

read from or written to the slave device).

The slave whose address corresponds to the transmitted

address responds by pulling SDA low during the ninth

clock pulse (this is termed the acknowledge bit). At this

stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its shift register.

Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during the

low period of SCL and remain stable during the high

period of SCL.

When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10th clock pulse to establish a

stop condition. In read mode, the master issues a No

Acknowledge for the ninth clock pulse (that is, the SDA

line remains high). The master then brings the SDA line

low before the 10th clock pulse and then high during the

10th clock pulse to establish a stop condition.

READ/WRITE SEQUENCE

In the case of the AD5305/AD5315/AD5325, all write access

sequences and most read sequences begin with the device

address (with R/W = 0) followed by the pointer byte. This

pointer byte specifies the data format and determines which

DAC is being accessed in the subsequent read/write operation

(see Figure 31). In a write operation, the data follows

immediately. In a read operation, the address is resent with

R/W = 1 and then the data is read back. However, it is also

possible to perform a read operation by sending only the

address with R/W = 1. The previously loaded pointer settings

are then used for the readback operation. See Figure 32 for a

graphical explanation of the interface.

DACD

LSB

MSB

DACC DACB DACA

Figure 31. Pointer Byte

POINTER BYTE BITS

Table 6 explains the individual bits that make up the pointer byte.

Table 6. Individual Bits of the Pointer Byte

Bit

Description

Don’t care bits.

Reserved bits. Must be set to 0.

DACD

[1] The following data bytes are for DAC D.

DACC

[1] The following data bytes are for DAC C.

DACB

[1] The following data bytes are for DAC B.

DACA

[1] The following data bytes are for DAC A.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide. Data is loaded into the

device as two data bytes on the serial data line, SDA, under the

control of the serial clock input, SCL. The timing diagram for

this operation is shown in Figure 2. The two data bytes consist

of four control bits followed by 8, 10, or 12 bits of DAC data,

depending on the device type. The first two bits loaded are the

PD1 and PD0 bits that control the mode of operation of the device.

See the Power-Down Modes section for a complete description.

Bit 13 is CLR, Bit 12 is LDAC, and the remaining bits are left

justified DAC data bits, starting with the MSB. See Figure 32.

DATA BYTES (WRITE AND READBACK)

MOST SIGNIFICANT DATA BYTE

PD0

PD1

LSB

PD0

CLR

LDAC

PD1

LSB

MSB

10-BIT AD5315

LSB

MSB

12-BIT AD5325

CLR

LDAC

MSB

8-BIT AD5305

CLR

LDAC

PD0

D11

D10

LEAST SIGNIFICANT DATA BYTE

LSB

MSB

10-BIT AD5315

LSB

MSB

12-BIT AD5325

MSB

8-BIT AD5305

Figure 32. Data Formats for Write and Readback

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