FG484 datasheet(121/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-107

Timing Characteristics

Figure 2-35 • Input DDR Timing Diagram

tDDRICLR2Q2

tDDRIREMCLR

tDDRIRECCLR

tDDRICLR2Q1

CLK

Data

CLR

Out_QR

Out_QF

tDDRICLKQ1

tDDRIHD

tDDRISUD

tDDRICLKQ2

Table 2-181 • Input DDR Propagation Delays

Military-Case Conditions: TJ = 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L

Parameter

Description

–1

Std.

Units

tDDRICLKQ1

Clock-to-Out Out_QR for Input DDR

0.38

0.45

tDDRICLKQ2

Clock-to-Out Out_QF for Input DDR

0.54

0.63

tDDRISUD1

Data Setup for Input DDR (fall)

0.39

0.46

tDDRISUD2

Data Setup for Input DDR (rise)

0.34

0.40

tDDRIHD1

Data Hold for Input DDR (fall)

0.00

tDDRIHD2

Data Hold for Input DDR (rise)

0.00

tDDRICLR2Q1

Asynchronous Clear-to-Out Out_QR for Input DDR

0.64

0.75

tDDRICLR2Q2

Asynchronous Clear-to-Out Out_QF for Input DDR

0.79

0.93

tDDRIREMCLR

Asynchronous Clear Removal Time for Input DDR

0.00

tDDRIRECCLR

Asynchronous Clear Recovery Time for Input DDR

0.31

0.36

tDDRIWCLR

Asynchronous Clear Minimum Pulse Width for Input DDR

0.19

0.22

tDDRICKMPWH

Clock Minimum Pulse Width HIGH for Input DDR

0.31

0.36

tDDRICKMPWL

Clock Minimum Pulse Width LOW for Input DDR

0.28

0.32

FDDRIMAX

Maximum Frequency for Input DDR

TBD

MHz

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

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