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FG484 Datasheet(PDF) 138 Page - Microsemi Corporation

Part # FG484
Description  Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology
PDF  212 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

FG484 Datasheet(HTML) 138 Page - Microsemi Corporation

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Military ProASIC3/EL DC and Switching Characteristics
2-124
Revision 3
Table 2-198 • A3P250 Global Resource
Military-Case Conditions: TJ = 125°C, VCC = 1.425 V
Parameter
Description
–1
Std.
Units
Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.97
1.24
1.14
1.46
ns
tRCKH
Input High Delay for Global Clock
0.94
1.27
1.11
1.49
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.32
0.38
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating
values.
Table 2-199 • A3P1000 Global Resource
Military-Case Conditions: TJ = 125°C, VCC = 1.425 V
Parameter
Description
–1
Std.
Units
Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
1.18
1.44
1.39
1.70
ns
tRCKH
Input High Delay for Global Clock
1.17
1.48
1.37
1.74
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.32
0.37
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-8 for derating
values.



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